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aes02173 m p-dso-28-6 enhanced power 1-a hex-half-bridge / double six-driver tle 5208-6 g semiconductor group 1 1998-02-01 description the tle 5208-6 g is a fully protected hex - h alf- b ridge- d river designed specifically for automotive and industrial motion control applications. the part is based on the siemens power technology spt ? which allows bipolar and cmos control circuitry in accordance with dmos power devices existing on the same monolithic circuitry. the six low and high side drivers are free configurable and can be controlled separately. therefore all kind of loads can be combined. in motion control up to 5 actuators (dc-motors) can be connected to the 6 half-bridge-outputs (cascade configuration). operation modes forward (cw), reverse (ccw), brake and high impedance are controlled from a standard spi-interface. the possibility to control the outputs via software from a central logic, allows limiting the power dissipation. so the standard p-dso-28-6- package meets the application requirements and saves pcb-board-space and cost. furthermore the build-in features like over- and under-voltage-lockout, over- temperature-protection and the very low quiescent current in stand-by mode opens a wide range of automotive- and industrial-applications. type ordering code package tle 5208-6 g q67007-a9282 p-dso-28-6 overview features ? six high-side and six low-side-drivers ? free configurable as switch, half-bridge or h-bridge ? optimized for dc motor management applications ? 0.6 a continuous (1 a peak) current per switch ? r ds on ; typ.1 w , @ 25 c per switch ? output: short-circuit protected and diagnosis ? over-temperature-protection with hysteresis and diagnosis ? standard spi-interface ? very low current consumption (typ. 20 m a, @ 25 c) in stand-by (inhibit) mode ? over- and under-voltage-lockout ? cmos/ttl compatible inputs with hysteresis ? no crossover current ? internal clamp diodes ? enhanced power p-dso-package
tle 5208-6 g semiconductor group 2 1998-02-01 figure 1 pin configuration (top view) aep02174 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 leadframe chip s v out l5 out h5 out h4 out l4 gnd gnd gnd gnd v s l2 out h2 out h3 out out l3 out h6 out l6 out h1 l1 out cc v di clk csn gnd gnd gnd gnd do inh
tle 5208-6 g semiconductor group 3 1998-02-01 pin definitions and functions pin no. symbol function 1outl5 low-side-output 5 ; power-mos open drain with internal reverse diode; no internal clamp diode or active zenering; short-circuit protected and open load controlled. 2outh5 high-side-output 5 ; power-mos open source with internal reverse diode; no internal clamp diode or active zenering; short-circuit protected and open load controlled. 3outh4 high-side-output 4 ; see pin2. 4outl4 low-side-output 4 ; see pin1. 5 v s power supply ; external connection to pin 10 necessary; needs a blocking capacitor as close as possible to gnd; value: 22 m f electrolytic in parallel to 220 nf ceramic. 6, 7, 8, 9 gnd ground; reference potential; internal connection to pin 20, 21, 22 and 23; cooling tab; to reduce thermal resistance; place cooling areas on pcb close to this pins. 10 v s power supply ; see pin 5. 11 outl3 low-side-output 3 ; see pin1. 12 outh3 high-side-output 3 ; see pin2. 13 outh2 high-side-output 2 ; see pin2. 14 outl2 low-side-output 2 ; see pin1. 15 outh1 high-side-output 1 ; see pin2. 16 outl1 low-side-output 1 ; see pin1. 17 inh inhibit input; has an internal pull down; device is switched in standby condition by pulling the inh terminal low. 18 do serial-data-output; this 3-state output transfers diagnosis data to the control device; the output will remain 3-stated unless the device is selected by a low on chip-select-not (csn); see table at page 8 for diagnosis protocol. 19 v cc logic supply voltage ; needs a blocking capacitor as close as possible to gnd; value: 10 m f electrolytic in parallel to 220 nf ceramic.
tle 5208-6 g semiconductor group 4 1998-02-01 20, 21, 22, 23 gnd ground 24 csn chip-select-not input ; csn is an active low input; serial communication is enabled by pulling the csn terminal low; csn input should only be transitioned when clk is low; csn has an internal active pull up and requires cmos logic level inputs. 25 clk serial clock input ; clocks the shiftregister; clk has an internal active pull down and requires cmos logic level inputs. 26 di serial data input; receives serial data from the control device; serial data transmitted to di is an 16-bit control word with the least significant bit (lsb) being transferred first: the input has an active pull down and requires cmos logic level inputs; di will accept data on the falling edge of clk-signal; see table at page 8 for input data protocol. 27 outl6 low-side-output 6 ; see pin1. 28 outh6 high-side-output 6 ; see pin2. pin definitions and functions (contd) pin no. symbol function
tle 5208-6 g semiconductor group 5 1998-02-01 figure 2 block diagram circuit description figure 2 shows a block schematic diagram of the module. there are 6 half-bridge-drivers on the right-hand side. an hs driver and an ls driver are combined to form a half-bridge-driver in each case. the drivers communicate via the internal data bus with the logic and the other control and monitoring functions: under-voltage (uv), over-voltage (ov), over-temperature (tsd), charge pump and fault detect. two connection interfaces are provided for supply to the module: all power drivers are connected to the supply voltage v s . these are monitored by over-voltage and under- 1 drv6 drv5 drv4 drv3 drv2 drv1 28 out h6 27 out l6 l5 out 1 h5 out 2 3 out h4 4 out l4 l3 out 11 h3 out 12 23 22, 8, 9, 21, 20, 7, 6, 13 out h2 14 out l2 l1 out 16 h1 out 15 10 5, s cc 19 17 inh latch and logic bit 16 5208-6 g tle tsd ov uv detect pump charge fault- bias inhibit spi 25 24 clk csn di do 26 18 vv gnd aeb02175 _ <
tle 5208-6 g semiconductor group 6 1998-02-01 voltage comparators with hysteresis, so that the correct function can be checked in the application at any time. the logic is supplied by the v cc voltage, typ. with 5 v. the v cc voltage uses an internally generated power-on reset (por) to initialize the module at power-on. the advantage of this system is that information stored in the logic remains intact in the event of short- term failures in the supply voltage v s . the system can therefore continue to operate following v s under-voltage, without having to be reprogrammed. the under-voltage information is stored, and can be read out via the interface. the same logically applies for over-voltage. interference spikes on v s are therefore effectively suppressed. the situation is different in the case of under-voltage on the v cc connection pin. if this occurs, then the internally stored data is deleted, and the output levels are switched to high-impedance status (tristate). the module is initialized by v cc following restart (power-on reset = por). the 16-bit wide programming word or control word (see table at page 8 ) is read in via the di data input, and this is synchronized with the clock input clk. the status word appears synchronously at the do data output (see table at page 8 ). the transmission cycle begins when the chip is selected with the csn input (h to l). if the csn input changes from l to h then the word which has been read-in becomes the control word. the do output switches to tristate status at this point, thereby releasing the do bus circuit for other uses. the inh inhibit input can be used to cut off the complete module. this reduces the current consumption to just a few m a, and results in the loss of any data stored. the output levels are switched to tristate status. the module is reinitialized with the internally generated por (power-on reset) at restart. this feature allows the use of this module in battery-operated applications (vehicle body control applications). every driver block from drv 1 to 6 contains a low-side driver and a high-side driver. the output connections have been selected so that each hs driver and ls driver pair can be combined to form a half-bridge by short-circuiting adjacent connections. the full flexibility of the configuration can be achieved by dissecting the half-bridges into quarter-bridges. figure 3 shows examples of possible applications. when commutating inductive loads, the dissipated power peak can be significantly reduced by activating the transistor located parallel to the internal freewheeling diode. a special, integrated timer for power on/off times ensures there is no crossover current at the half-bridge.
tle 5208-6 g semiconductor group 7 1998-02-01 figure 3 configuration examples for quarter bridges on the tle 5208-6 g aes02176 hs driver driver ls gnd outh1 to 6 outl1 to 6 load load load load m m 1/6 tle 5208-6 g high-side switch and low-side switch with internal freewheeling for slow commutating high-side switch with external freewheeling for slow commutating for fast commutating with external freewheeling low-side switch full-bridge motor control; motors connected halfbridge driver) (saves a complete in series; s v
tle 5208-6 g semiconductor group 8 1998-02-01 input data protocol diagnosis data protocol bit bit 15 ovlo on/off 15 power supply fail 14 not used 14 underload 13 overcurrent sd on/off 13 overload 12 hs-switch 6 12 status hs-switch 6 11 ls-switch 6 11 status ls-switch 6 10 hs-switch 5 10 status hs-switch 5 9 ls-switch 5 9 status ls-switch 5 8 hs-switch 4 8 status hs-switch 4 7 ls-switch 4 7 status ls-switch 4 6 hs-switch 3 6 status hs-switch 3 5 ls-switch 3 5 status ls-switch 3 4 hs-switch 2 4 status hs-switch 2 3 ls-switch 2 3 status ls-switch 2 2 hs-switch 1 2 status hs-switch 1 1 ls-switch 1 1 status ls-switch 1 0 status register reset 0 temp. prewarning h= on l= off h= on l= off
tle 5208-6 g semiconductor group 9 1998-02-01 fault result table fault diag.-bit result overcurrent (load) 13 only the failed output is switched off. function can be deactivated by bit no. 13. short-circuit to gnd (high-side-switch) 13 only the failed output is switched off. function can be deactivated by bit no. 13. short-circuit to v s (low-side-switch) 13 only the failed output is switched off. function can be deactivated by bit no. 13. temperature warning 0 reaction of control device needed. temperature shut down (sd) C all outputs off. openload 14 reaction of control device needed. underload 14 reaction of control device needed. under-voltage- lockout (uvlo) 15 all outputs off. over-voltage-lockout (ovlo) 15 all outputs off. function can be deactivated by bit no. 15. h = failure; l = no failure.
tle 5208-6 g semiconductor group 10 1998-02-01 electrical characteristics note: maximum ratings are absolute ratings; exceeding any one of these values may cause irreversible damage to the integrated circuit. absolute maximum ratings parameter symbol limit values unit remarks min. max. voltages supply voltage v s C 0.3 40 v C supply voltage v s C 1 C v t < 0.5 s; i s > C 2 a logic supply voltage v cc C 0.3 7 v 0 v < v s < 40 v logic input voltages (di, clk, csn, inh) v i C 0.3 7 v 0 v < v s < 40 v 0 v < v cc < 7 v logic output voltage (do) v do C 0.3 v cc v0 v < v s < 40 v 0 v < v cc < 7 v currents output current (cont.) i out1-6 C C a internal limited; see overcurrent section output current (peak) i out1-6 C C a internal limited; see overcurrent section temperatures junction temperature t j C 40 150 cC storage temperature t stg C 50 150 cC
tle 5208-6 g semiconductor group 11 1998-02-01 operating range parameter symbol limit values unit remarks min. max. supply voltage v s v uv off 40 v after v s rising above v uv on supply voltage slew rate d v s / d t C10v/ m sC logic supply voltage v cc 4.75 5.5 v C supply voltage increasing v s C 0.3 v uv on v outputs in tristate supply voltage decreasing v s C 0.3 v uv off v outputs in tristate logic input voltage (di,clk,csn,inh) v i C 0.3 v cc vC spi clock frequency f clk C1mhzC junction temperature t j C 40 150 cC thermal resistances junction pin r thj-pin C 25 k/w measured to pin 7 junction ambient r thja C65k/wC
tle 5208-6 g semiconductor group 12 1998-02-01 electrical characteristics 8v< v s < 40 v; 4.75 v < v cc < 5.25 v; inh = high; all outputs open; C 40 c< t j < 150 c; unless otherwise specified parameter symbol limit values unit test condition min. typ. max. current consumption quiescent current i s C2050 m ainh= low; v s = 13.2 v quiescent current i s C2030 m ainh= low; v s = 13.2 v; t j = 25 c logic-supply current i cc CC20 m ainh = low logic-supply current i cc C2.56maall hs-switches on supply current i s C25maC over- and under-voltage lockout uv-switch-on voltage v uv on C6.57v v s increasing uv-switch-off voltage v uv off 5.56Cv v s decreasing uv-on/off-hysteresis v uv hy C0.5Cv v uv on C v uv off ov-switch-off voltage v ov off 34 37 40 v v s increasing ov-switch-on voltage v ov on 28 32 36 v v s decreasing ov-on/off-hysteresis v ov hy C5Cv v ov off C v ov on
tle 5208-6 g semiconductor group 13 1998-02-01 outputs outh1-6 and outl1-6 static drain-source-on resistance source (high-side) i out = C 0.5 a r ds on h C11.5 w 8v < v s < 40 v t j = 25 c C2.5 w 8v < v s < 40 v 2C w v soff < v s 8v t j = 25 c C4 w v soff < v s 8v sink (low-side) i out = 0.5 a r ds on l C11.5 w 8v < v s < 40 v t j = 25 c C2.5 w 8v < v s < 40 v 2C w v soff < v s 8v t j = 25 c C4 w v soff < v s 8v leakage current source-output-stage 1 to 6 i qlh C1CCma v outh1-6 = 0 v sink-output-stage 1 to 6 i qll CC1ma v outl1-6 = v s overcurrent source shutdown threshold i sdu C2 C1.5 C1 a C sink shutdown threshold i sdl 11.52aC current limit i ocl C35asink and source shutdown delay time t dsd 25 50 80 m s sink and source electrical characteristics (contd) 8v< v s < 40 v; 4.75 v < v cc < 5.25 v; inh = high; all outputs open; C 40 c< t j < 150 c; unless otherwise specified parameter symbol limit values unit test condition min. typ. max.
tle 5208-6 g semiconductor group 14 1998-02-01 open circuit detection current i ocd 10 40 100 ma C delay time t doc 200 350 500 m sC delay time from stand-by to data in setup time t set C C 100 m sC output delay times; v s = 13.2 v; r load = 25 w (device not in stand-by for t > 1 ms) source on t donh C520 m sC source off t doffh C420 m sC sink on t donl C630 m sC sink off t doffl C210 m sC dead time t dhl 1CC m s t donl C t doffh dead time t dlh 1 CC m s t donh C t doffl output switching times; v s = 13.2 v; r load = 25 w (device not in stand-by for t > 1 ms) source on t on h C630 m sC source off t off h C15 m sC sink on t on l C2.510 m sC sink off t off l C15 m sC clamp diodes forward voltage upper v fu C11.5v i f = 0.5 a lower v fl C11.5v i f = 0.5 a electrical characteristics (contd) 8v< v s < 40 v; 4.75 v < v cc < 5.25 v; inh = high; all outputs open; C 40 c< t j < 150 c; unless otherwise specified parameter symbol limit values unit test condition min. typ. max.
tle 5208-6 g semiconductor group 15 1998-02-01 inhibit input h-input voltage threshold v ih CC0.7 v cc C l-input voltage threshold v il 0.2 C C v cc C hysteresis of input voltage v ihy 50 200 500 mv C pull down current i i 10 25 50 m a v i = 0.2 v cc input capacitance c i C 1015pf0v < v cc < 5.25 v spi-interface logic inputs di, clk and csn h-input voltage threshold v ih CC0.7 v cc C l-input voltage threshold v il 0.2 C C v cc C hysteresis of input voltage v ihy 50 200 500 mv C pull up current at pin csn i icsn C50 C25 C10 m a v csn = 0.7 v cc pull down current at pin di i idi 10 25 50 m a v di = 0.2 v cc pull down current at pin clk i iclk 10 25 50 m a v clk = 0.2 v cc input capacitance at pin csn, di or clk c i C 1015pf0v < v cc < 5.25 v logic output do h-output voltage level v doh v cc C 1.0 v cc C 0.7 Cv i doh =1 ma l-output voltage level v dol C0.20.4v i dol = C 1.6 ma tristate leakage current i dolk C 10 C 10 m a v csn = v cc 0v < v do < v cc electrical characteristics (contd) 8v< v s < 40 v; 4.75 v < v cc < 5.25 v; inh = high; all outputs open; C 40 c< t j < 150 c; unless otherwise specified parameter symbol limit values unit test condition min. typ. max.
tle 5208-6 g semiconductor group 16 1998-02-01 tristate input capacitance c do C 1015pf v csn = v cc 0v < v cc < 5.25 v data input timing clock period t pclk 1000 C CnsC clock high time t clkh 500 C CnsC clock low time t clkl 500 C CnsC clock low before csn low t bef 500 C CnsC csn setup time t lead 500 C CnsC clk setup time t lag 500 C CnsC clock low after csn high t beh 500 C CnsC di setup time t disu 250 C CnsC di hold time t diho 250 C CnsC input signal rise time at pin di, clk and csn t rin C C 200 ns C input signal fall time at pin di, clk and csn t fin C C 200 ns C data output timing do rise time t rdo C 50 100 ns c l = 100 pf do fall time t fdo C 50 100 ns c l = 100 pf do enable time t endo C C 250 ns low impedance do disable time t disdo C C 250 ns high impedance do valid time t vado C 100 250 ns v do < 0.1 v cc ; v do > 0.9 v cc ; c l = 100 pf electrical characteristics (contd) 8v< v s < 40 v; 4.75 v < v cc < 5.25 v; inh = high; all outputs open; C 40 c< t j < 150 c; unless otherwise specified parameter symbol limit values unit test condition min. typ. max.
tle 5208-6 g semiconductor group 17 1998-02-01 thermal prewarning and shutdown thermal prewarning junction temperature t jpw 120 145 170 c C temperature prewarning hysteresis d t C30 CkC thermal shutdown junction temperature t jsd 150 175 200 cC thermal switch-on junction temperature t jso 120 C 170 cC temperature shutdown hysteresis d t C30 CkC ratio of sd to pw temperature t jsd / t jpw 1.05 1.20 C C C electrical characteristics (contd) 8v< v s < 40 v; 4.75 v < v cc < 5.25 v; inh = high; all outputs open; C 40 c< t j < 150 c; unless otherwise specified parameter symbol limit values unit test condition min. typ. max.
tle 5208-6 g semiconductor group 18 1998-02-01 timing diagrams figure 4 data transfer timing aet02177 0 12 3 4 5 6 7 8910 11 12 13 14 15 0 1 ++ csn clk di do hs1 e.g. old data actual data time new data actual status csn high to low: do is enabled. status information transfered to output shift reg. csn low to high: data from shift-register is transfered to output power switches actual data prev. status di: will accept data on the falling edge of clk-signal do: will change state on the rising edge of clk-signal time time time time 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - - - - - - - -- 0 1
tle 5208-6 g semiconductor group 19 1998-02-01 figure 5 spi-input timing figure 6 turn off/on time aet02178 di valid don't care valid don't care don't care cc v 0.7 0.2 v cc bef t t lead clkh t t clkl beh t lag t t diho t disu clk csn cc v 0.2 0.7 v cc cc v 0.2 0.7 v cc aet02179 csn don t 10% 90% t rin fin t off t doff t off state on state off state on state on t case 1 case 2 i out out i 50% 50% 90% 10% 10% 90% 50%
tle 5208-6 g semiconductor group 20 1998-02-01 figure 7 do valid data delay time and valid time figure 8 do enable and disable time aet02180 clk t rin fin t (low to high) rdo t do do (high to low) fdo t t vado 10 ns 50% cc v 0.9 0.1 v cc cc v 0.9 v cc 0.1 cc v 0.9 v cc 0.1 _ < aet02181 csn t fin rin t do do 10 ns t endo endo t disdo t t disdo v cc to pullup pulldown to gnd 10 k w 50% 50% 50% 0.9 v cc cc v 0.1 _ < 10 k w
tle 5208-6 g semiconductor group 21 1998-02-01 figure 9 application circuit aes02182 18 26 do di csn clk 24 25 spi inhibit bias fault- charge pump detect uv ov tsd 16 bit logic and latch inh 17 19 cc vv s 5, 10 15 out h1 16 out l1 14 13 6, 7, 20, 21, 8, 9, 22, 23, gnd 12 11 4 3 2 1 27 28 gnd p watchdog reset q tle 4268g d 100 nf d c wd r cc v c q 22 f i 10 f s c d02 z39 = 12 v v s drv1 drv2 drv3 drv4 drv5 drv6 d01 1n4001 1 m1 m2 m3 m4 m5 tle 5208-6 g m _ < out h2 out h3 out h4 out h5 out l2 out l3 out l4 out h6 out l5 out l6 m m
tle 5208-6 g semiconductor group 22 1998-02-01 package outlines p-dso-28-6 (plastic dual small outline package) 114 15 28 18.1 -0.4 index marking 1) 2.45 -0.1 7.6 10.3 0.3 -0.2 0.2 2.65 max -0.2 1.27 0.23 +0.09 0.1 0.4 0.35 x 45? +0.8 +0.15 0.35 2) 8? max 0.2 28x 1) 2) does not include dambar protrusion of 0.05 max per side 1) does not include plastic or metal protrusions of 0.15 max rer side gps05123 sorts of packing package outlines for tubes, trays etc. are contained in our data book package information. dimensions in mm smd = surface mounted device

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